A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to implement vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes transistor/memory-cell pillars extending through openings in repeating conductive structures/insulative structures (e.g., tiers), where the conductive structures function as control gates. The vertically stacked tiers of conductive structures (e.g., word line plates, control gate plates) and insulative structures at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upward (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include electrical connections between the conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such an electrical connection includes forming a so-called “staircase” structure having a series of so-called “stairs” at laterally offset edges (e.g., lateral ends) of the tiers of conductive structures. The individual stairs define contact regions of the conductive structures upon which contact structures can be positioned to provide electrical access to the conductive structures. Various processes of forming staircase structures have been developed, including repeatedly trimming a photoresist material and etching exposed regions of the conductive structures through the trimmed photoresist material to form the stairs at lateral ends of the tiers. This process is referred to herein as a trim-etch-trim process. The trim-etch-trim process creates multiple stair-like steps in the alternating conductive structures and insulating structures, which results in the staircase structure. A stepped profile is formed by patterning the lateral ends, such as peripheral edges, of the tiers. The trim-etch-trim process requires the photoresist material to be deposited at a sufficient thickness to survive the multiple trim acts and etch acts that are conducted. As the number of stairs in a staircase structure increases, the thickness of the photoresist material is increased accordingly to provide sufficient margin for the multiple trim acts and etch acts. However, the increased thickness of the photoresist material increases locational and dimensional error associated with the formation of the stairs. The increased thickness of the photoresist material also leads to problems with edge placement and line width roughness (LWR) of the conductive structures/insulative structures.
To provide electrical connections to both shallow conductive structures and deep conductive structures, openings having different depths are formed through the conductive structures and insulative structures. Since the conductive structures are located at different depths, the openings are formed at various depths to contact (e.g., land on) the individual stairs. To ensure that the openings are formed to the desired depths, an etch process is conducted to form the openings down to the deep conductive structures. However, the amount of time and other conditions of the etch process increase the likelihood that the openings to the shallow conductive structures will be overetched (e.g., punched through) into the underlying conductive structures. Contact structures subsequently formed in such openings land unreliably on the conductive structures, which causes failure of a device including the staircase structure.